Welcome to S-Link’s documentation!

Contents:

• Overview
  • Document Organization
  • Motivation
  • Why Chiplets?
    • Possible Example Chiplet
    • The Future of Hardware Design (?)
• High Level Overview
  • Features
    • Multi-Lane Support
    • Application Data Width
    • Link Attributes
    • Low Power P States
• Packets
  • Short Packets
  • Long Packets
  • Reserved Data IDs
• Integration
  • Parameters
  • Ports
  • Application Layer Signaling
    • Long Packet Example
    • Short Packet Example
• LTSSM
  • 128b/130b Encoding
  • LTSSM States
    • IDLE
    • WAIT_CLK
    • SWITCH
    • P0_TS1
    • P0_TS2
    • P0_SDS
    • P0
    • ATTR_ST
    • PX_REQ_ST
    • PX_START_ST
    • P0_EXIT
    • P1
    • P2
    • P3
    • RESET
  • Internal Ordered Sets
    • SYNC
    • TS1
    • TS2
    • SDS
    • P-Req
      • P1 Req
      • P2 Req
      • P3 Req
      • PStart
    • Attribute OS
      • Attribute WRITE
      • Attribute READ
  • Power State Handshake
  • Reset / Wake Sideband Signals
    • Reset Condition
    • Hard Reset Condition
    • Wake Condition
• Link Layer Logic
  • slink_ll_tx
  • slink_ll_rx
  • Byte Stripping
  • CRC
  • ECC
• Testbench
  • simulate.sh
  • Testbench Defines
  • SerDes Model
  • slink_app_driver
    • sendRandomShortPacket
    • sendRandomLongPacket
    • sendShortPacket
    • sendLongPacket
  • slink_app_monitor
  • Tests
    • sanity_test
    • pstate_sanity
    • random_packets
    • link_width_change
    • slink_force_reset
    • slink_force_hard_reset
    • ecc_correction
    • ecc_corruption
  • Regressions
• Attributes
  • S-Link Attributes
• SLINK_CTRL Registers
  • SWRESET
  • ENABLE
  • INTERRUPT_STATUS
  • INTERRUPT_ENABLE
  • PSTATE_CONTROL
  • ERROR_CONTROL
  • COUNT_VAL_1US
  • SHORT_PACKET_MAX
  • SW_ATTR_ADDR_DATA
  • SW_ATTR_CONTROLS
  • SW_ATTR_DATA_READ
  • SW_ATTR_FIFO_STATUS
  • SW_ATTR_SHADOW_UPDATE
  • SW_ATTR_EFFECTIVE_UPDATE
  • STATE_STATUS
  • DEBUG_BUS_CTRL
  • DEBUG_BUS_STATUS
• Synthesis/PnR
• Roadmap