RoadmapΒΆ

This is a tentative roadmap for the S-Link project. Here are some of the main items I wish to acheive in the next 6-8 months. Based on feedback and uses, some of these may move around in the timeline.

  • AXI Application Layer

    • A configurable AXI application layer that can allow commuinication between chips using AXI

    • Address and Data width would be configurable

  • 8/16/32/64 lane support

  • 128/130b encoding support

  • Phy backpressure support

  • 32bit PHY_DATA_WIDTH support

  • CPI Application Layer

  • TileLink Application Layer

_images/roadmap.png